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FPGA Architect/Integrator

Job Description

We have a current opportunity for a FPGA Architect/Integrator on a contract basis, for a MINIMUM of 12 months in Sweden

Assignment Description and Requirements

As a FPGA Architect and Integrator of FPGA design team, you will play a central role in driving Architecture based on specifications, integration of whole FPGA (IPs and design blocks, data bus design, clock and reset circuit etc.), place/route and timing closure. The individual will be responsible for analyzing design spec, architecture, code review of desig blocks, participating in test plan reviews and participating in lab bring-up and debugging.

Key Qualifications

  • Integration of full design comprising of IPs and design blocks in Xilinx/Altera FPGAs
  • Maintain common design platform FPGA, with considerations for memories, I/Os, gated clocks and complex generated clocks.
  • Design and verification using Verilog/System Verilog/VHDL
  • Perform FPGA Synthesis, Place & Route, timing optimizations
  • Perform bring-up, debug, and validation of designs to achieve functional and performance goals
  • Create and execute plans to bring-up, debug, and validate designs
  • Thoroughly document and support each of above steps
  • Collaborate with cross-functional teams in order to define prototype hardware to evaluate new technologies and features
  • Experience in telecom domain (Radio, Baseband) preferred
  • Experience in high speed FPGA design (in excess of 492 MHz)

Additional technical skills:

  • Multi-core environment, embedded system background knowledge
  • Good mathematical skills
  • Low level/platform programming & debugging tools knowledge
  • Good programming skills with script languages (e.g. Python, Perl, Unix shell)
  • Pronto, Jira tool, ClearCase, Doors


Typically requires a minimum of 8-10 years of experience with bring up, debugging and verification on FPGA In depth experience with FPGA platforms: Xilinx FPGA boards, debug, performance and throughput tuning In depth knowledge of top down FPGA development process Solid understanding of the tool flow from RTL to bitstream Hands on lab bring-up experience, debug, and instrument usage Proven design validation skills Proven micro architecture development and excellent documentation skills In depth experience writing Verilog code. Experience with System Verilog verification environments Good analytical skills Experience on Python/Tcl scripting is plus.

  • Excellent oral and written English skills
  • Education & Experience
  • BSEE, MSEE with industry experience over 8 years.